The present invention relates to a method for fabricating integrated circuits. More particularly, it relates to a novel method for forming a self-supporting separable silicon mask and for utilizing such a silicon mask in the fabrication of integrated circuits.
Integrated circuits are conventionally formed by photolithographic fabrication techniques wherein a photoresist pattern must be formed on the integrated circuit substrate prior to virtually every fabrication step involving the definition of a particular lateral pattern on the substrate. The photoresist defines various metallic patterns formed during the fabrication by photolithographic etching or, similarly, it is used to form the pattern in the insulative layers or barrier layers used to limit the introduction of conductivity-determining impurities into the substrate or to limit areas of electrical insulation.
The fabrication of any standard large scale integrated circuit at the level of present technology requires dozens of such photolithographic masking steps. Each of said steps is complex in that it first involves the formation of a separable mask through which the photoresist layer is exposed, e.g., a conventional metal glass mask, followed by exposure of the photoresist to light through this mask and then development of the photoresist. In addition, each of such photoresist exposure steps requires a rather difficult alignment of the glass mask with the substrate. Part of the difficulty for such an alignment is that the alignment must be made between an alignment indicating mark on the substrate and one on the underside of the glass mask. The image of these alignment indicators must pass through from 50 to 60 mils thickness of glass before reaching the alignment microscope objective lens. This substantial distance between the alignment mark and the objective lens gives rise to optical aberration in alignment. Also, the image of the substrate alignment indicator must pass up through the photoresist layer covering the substrate which results in some aberration due to dispersion of light within the photoresist.
It would, thus, be desirable to have a method of integrated circuit fabrication wherein the utilization of photolithographic techniques were eliminated, and each of the integrated circuit fabrication steps could instead be performed with a separable mask which would serve to define the lateral geometries involved in that particular step. Silicon would be a desirable material for such separable masks in that it would have an identical thermal coefficient of expansion with the substrate and, thus, there would be no mask distortion during integrated fabrication steps requiring the application of heat.
In this respect, the use of silicon masks in the fabrication of integrated circuit elements by ion implantation has been disclosed in U.S. Pat. No. 3,713,922, Lepselter et al. However, such mask structures have relatively small utilizable masking portions or windows of thin silicon with a substantial portion of the mask being occupied by the array of thick silicon supporting ribs. As set forth in this patent, the windows of thin silicon (1 micron in thickness) have lateral dimensions of 50 to 500 microns and are supported by an array of ribs about 1 mil or 25 microns in thickness.
However, since standard large scale integrated circuits require chips having lateral dimensions in the order of 1250 microns to 12,500 microns and even greater, the structures shown in the patent do not appear to be capable of providing silicon masks with thin portions having corresponding dimensions in the order of from 1250 to 12,500 microns so that each window can mask a whole chip.